Fabrication of multilayer thin film interconnect structures for high-density integrated circuits generally involves sequential build of metal-patterned dielectric layers on silicon or ceramic substrates. Among the various dielectric/insulator materials which are generally used in the thin film structures, are sputtered or Plasma Enhanced Chemical Vapor Deposition (PECVD) quartz, silicon nitride, and high-temperature stable polymers, especially polyimides. The most commonly used high-conductivity metallurgies are aluminum/copper, gold, and/or copper.
The approach based on sequential building of each layer to form high-density wiring structures, however, suffers from the problem that every time a new layer is fabricated, the previously built layers are exposed to the entire process excursions including thermal, chemical/solvents, mechanical and other stress-related operations.
In addition, since the electrical performance and long-term reliability of the sequentially built structure can only be determined after the conclusion of the entire fabrication process, the finished part may have to be discarded if the performance does not meet the required specifications. This results in high cost of production, and has other obvious limitations in terms of cycle time/throughput.
When using polyimide dielectric (or other high-temperature polymers), an alternate approach to thin film interconnect structures is based on the assembly of individual electrically testable metallized thin films (layers) which are laminated at high temperature such that metal/metal and polymer/polymer bonding can be achieved.
This method eliminates some of the limitations of the sequential process, as each metallized dielectric layer is fabricated as a single unit which can be fully tested for the desired electrical characteristics. Then each of these layers are stacked to form multiple layers and laminated under heat and pressure.
Although this method would be potentially superior to sequential build, it has a fundamental concern with regard to the dimensional stability of the structure during both individual layer build and during the joining of the individual layers to form the composite multilayer structure. This is due to the fact that the thin polymer films, such as polyimide films, are generally fragile and flexible, and are subject to deformation under thermal or solvent-related stress conditions. This can result in pattern misalignment/distortion during layer fabrication or in the process of lamination and also when the composite structure undergoes accelerated reliability tests involving temperature and humidity excursions.
A recent Japanese Patent Application No. 63-274199 (1988) entitled "Multilayer Wiring Formation Method" discloses individual build of layers, comprising polyimide insulator with copper wiring and copper/gold interface metal. This method is based on metal patterning of partially cured polyimide layers formed on a substrate, after which the layers are peeled off from the substrate, smoothed by vacuum, stacked, and then laminated in one step by heating under pressure. During this process, interlayer bonding occurs due to polymer interdiffusion at the interface which is also accompanied by full polymer cure, and at the same time gold/gold joining causes metal interconnections. However, the process according to this process would suffer the limitations of potential pattern misalignment/distortion mentioned above.
The following references relate generally to methods of forming metallurgical patterns in insulator films:
U.S. Pat. No. 2,692,190, issued to N. Pritikin (1954) discloses a method for generating embedded metallurgy to fabricate printed circuits having large dimensions on a temporary base plate which is removed by chemical etching every time. After the conductor pattern is defined, and an insulator such as Teflon, polystyrene etc., is applied, the base plate is removed by a selective etching process.
Another U.S. Pat. No. 3,181,986, issued to N. Pritikin, (1965) also relates to printed circuits. The primary difference between this Patent and U.S. Pat. No. 2,692,190, is that the temporary base plate is not consumed each time and thus the process is less expensive.
U.S. Pat. No. 3,466,206, issued to J. T. Beck, (1969) also relates to a method of making embedded printed circuits, having integral aligned through terminals exposed on both sides by a subtractive etch process. The metal sheet can be copper, silver, gold, brass, stainless steel etc., and the insulator is a thermosetting or cold-setting resin, self-hardening resin or one which requires heat and pressure for cure, including epoxies, phenolics, melamine, Teflon, or composites with glass fillers.
U.S. Pat. No. 3,541,222, issued to H. L. Parks, et al., (1970) discusses a connector screen or "interposer" comprising conductive connector elements embedded in a deformable insulator such that the conductive elements are protruding from both sides.
U.S. Pat. No. 4,604,160, issued to K. Murakami et al., (1986) discloses a method for fabricating a flexible printed wiring board with emphasis on the adhesion of the plating resist and the conductor pattern during the plating process.
U.S. Pat. No. 4,707,657, issued to A. Boegh-Petersen, (1987) is concerned with double-sided printed circuit boards of a connector assembly, thin film and thick film circuit board, and multilayer circuit board.
U.S. patent application, Ser. No. 07/503,401, filed Mar. 30, 1990, now U.S. Pat. No. 5,115,090 and assigned to the assignee of the present Patent Application, the disclosure of which is incorporated herein by reference, describes low thermal expansion polyimides with special properties for use as a polymer dielectric and/or passivation layer in fabricating multilayer metal structures.